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A completely integrated single-chip PLL with a 34 GHz VCO using 0.2 mu m E-/D-HEMT-technology

Eine vollständig integrierte Einchip-PLL mit 34 GHz VCO auf der Basis einer 0.2 Mikrometer E-/D-HEMT-Technologie

: Lang, M.; Leber, P.; Wang, Z.-G.; Lao, Z.; Rieger-Motzer, M.; Bronner, W.; Hülsmann, A.; Kaufel, G.; Raynor, B.

DOI: 10.1109/CICC.1997.606682

	Institute of Electrical and Electronics Engineers -IEEE-: IEEE Custom Integrated Circuits Conference 1997. Proceedings Piscataway/N.Y.: IEEE Order Department, 1997 ISBN: 0-7803-3669-0 ISBN: 0-7803-3670-4 ISBN: 0-7803-3671-2 pp.529-532 : Ill.
	Custom Integrated Circuits Conference (CICC) <19, 1997, Santa Clara/Calif.>

	English
	Conference Paper
	Fraunhofer IAF ()
	PLL 34 GHz

Abstract
A completely integrated single-chip phase locked loop based on a 0.2 mu m gate length enhancement / depletion AlGaAs/GaAs/ AlGaAs-HEMT technology has been designed and characterized. The chip contains a VCO with 34 GHz center frequency, a dynamic frequency divider by two, a static divider by eight, a phase detector. and a loop fitter.. The chip size is 2.0 x 1.5 mm2. The power consumption is 1.2 W at a supply voltage of -5.0 V. The locking range is approximately +- 700 MHz. The phase noise of locked PLL is -83 dBc/Hz at 100 kHz and -102 dBc/Hz at 1 MHz offset from the carrier frequency, respectively.