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  4. A completely integrated single-chip PLL with a 34 GHz VCO using 0.2 mu m E-/D-HEMT-technology
 
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1997
Conference Paper
Title

A completely integrated single-chip PLL with a 34 GHz VCO using 0.2 mu m E-/D-HEMT-technology

Other Title
Eine vollständig integrierte Einchip-PLL mit 34 GHz VCO auf der Basis einer 0.2 Mikrometer E-/D-HEMT-Technologie
Abstract
A completely integrated single-chip phase locked loop based on a 0.2 mu m gate length enhancement / depletion AlGaAs/GaAs/ AlGaAs-HEMT technology has been designed and characterized. The chip contains a VCO with 34 GHz center frequency, a dynamic frequency divider by two, a static divider by eight, a phase detector. and a loop fitter.. The chip size is 2.0 x 1.5 mm2. The power consumption is 1.2 W at a supply voltage of -5.0 V. The locking range is approximately +- 700 MHz. The phase noise of locked PLL is -83 dBc/Hz at 100 kHz and -102 dBc/Hz at 1 MHz offset from the carrier frequency, respectively.
Author(s)
Lang, M.
Leber, P.
Wang, Z.-G.
Lao, Z.
Rieger-Motzer, M.
Bronner, Wolfgang  
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Hülsmann, A.
Kaufel, G.
Raynor, B.
Mainwork
IEEE Custom Integrated Circuits Conference 1997. Proceedings  
Conference
Custom Integrated Circuits Conference (CICC) 1997  
DOI
10.1109/CICC.1997.606682
Language
English
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Keyword(s)
  • PLL 34 GHz

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