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CMOS-implementation of optimized 16-bit cordic-processors and evaluation tools

 

Proceedings of the U.R.S.I. International Symposium on Signals, Systems and Electronics
1989
pp.760-763
International Symposium on Signals, Systems and Electronics <1989, Erlangen>
English
Conference Paper
Fraunhofer IMS ()
CORDIC; digitale Signalverarbeitung; Signalprozessor

Abstract
This paper is devoted to recursive CORDIC processors with 16 bit fixed-point arithmetics. After the presentation of unified and specialized CORDIC sequences which result from a parameter optimization of the algorithm, results of numerical experiments will be given which help to specify the internal data format and a proper rounding procedure. These algorithms are implemented on a CMOS CORDIC chip with a recursive architecture and a parameter RAM that allows programming with different CORDIC sequences. Evaluation tools for two parallel operating CORDIC processors will be presented. They include a development system as well as software tools like an assembler, a debugger, and self test programs.

: http://publica.fraunhofer.de/documents/PX-7915.html