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  4. A CMOS-array-computer with on-chip communication hardware developed for massively parallel applications
 
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1991
Conference Paper
Title

A CMOS-array-computer with on-chip communication hardware developed for massively parallel applications

Abstract
We present a scalable MIMD computer system which was designed to be used as a neurocomputer. it is capable of emulating different types of neurons including complex biologically motivated models based on activity pulses, variable pulse transmission times, and multiple threshold learning rules. It is constructed as an array consisting of nodal computer chips, each containing an on-chip communication processor to realize a full global communication. Hence, not only neural networks featuring arbitrary topologies can be built but also wide range of non-neural processing applications can be implemented. As an example, we will show how to use our system in solving optimization problems using genetic algorithms, and how to program it for real time image processing using combination of neural nets, genetic algorithms, and classical image processing techniques.
Author(s)
Schwarz, Markus
Hosticka, Bedrich J.
Kesper, Martin
Richert, Peter
Scholles, Michael  
Mainwork
IEEE International Joint Conference on Neural Networks 1991  
Conference
International Joint Conference on Neural Networks (IJNN) 1991  
DOI
10.1109/IJCNN.1991.170386
Language
English
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Keyword(s)
  • genetic-algorithms

  • hardware-routing

  • image-processing

  • neural-networks

  • parallel-computers

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