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A CMOS-array-computer with on-chip communication hardware developed for massively parallel applications

: Schwarz, Markus; Hosticka, Bedrich J.; Kesper, Martin; Richert, Peter; Scholles, Michael


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Joint Conference on Neural Networks 1991
Piscataway/N.J.: IEEE, 1991
ISBN: 0-7803-0227-3
ISBN: 0-7803-0228-1
ISBN: 0-7803-0229-X
International Joint Conference on Neural Networks (IJNN) <1991, Singapore>
Conference Paper
Fraunhofer IMS ()
genetic-algorithms; hardware-routing; image-processing; neural-networks; parallel-computers

We present a scalable MIMD computer system which was designed to be used as a neurocomputer. it is capable of emulating different types of neurons including complex biologically motivated models based on activity pulses, variable pulse transmission times, and multiple threshold learning rules. It is constructed as an array consisting of nodal computer chips, each containing an on-chip communication processor to realize a full global communication. Hence, not only neural networks featuring arbitrary topologies can be built but also wide range of non-neural processing applications can be implemented. As an example, we will show how to use our system in solving optimization problems using genetic algorithms, and how to program it for real time image processing using combination of neural nets, genetic algorithms, and classical image processing techniques.