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Circuit comparison by hierarchical pattern matching

: Pelz, G.DT Conference


9th IEEE International Conference on Computer-Aided Design '91. Digest of Technical Papers
Washington/D.C.: IEEE Computer Society Press, 1991
International Conference on Computer Aided Design <9, 1991, Santa Clara/Calif.>
Conference Paper
Fraunhofer IMS ()
Computer Aided Design (CAD); circuit comparison; hierarchical pattern matching; pattern matching; verification; VLSI

We present a new approach to circuit comparison and building-block recognition. In contrast to conventional systems, we employ netlist pattern matching as the basic feature, allowing to identify arbitrary subcircuits in larger circuits. Typically, a hierarchical netlist derived from a schematic and a flat netlist extracted from a layout have to be compared. In our approach, this is accomplished by the successive (bottom up) matching of the schematic cells in layout-netlist, thus restoring the schematic hierarchy. The pattern matching algorithm is embedded in a sophisticated hierarchy handling scheme, allowing to process even ill-structured hierarchies. Our method is independent from circuit technology and design style. Typical drawbacks of traditional systems as the handling of parallel pathes or the permutability of (groups of) terminals are overcome in a quite natural way.