BiCMOS circuits for DPCM coders in HDTV systems

Prototype chips have been designed and fabricated which prove that a 2.5 micrometer BiCMOS process is feasible for implementation of DPCM coders operating at HDTV clock frequencies, i.e. 54 MHz. As a part of the DPCM, a BiCMOS sequencer with 64 product terms runs at 80 MHz with 125 mW power consumption.