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BiCMOS circuits for DPCM coders in HDTV systems

: Eßer, W.; Hosticka, B.J.; Rothermel, A.; Schardein, W.; Tröster, G.

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Solid-State Circuits Conference 1990. Digest of technical papers
New York/N.Y., 1990
International Solid-State Circuits Conference <37, 1990, New York/N.Y.>
Conference Paper
Fraunhofer IMS ()
BICMOS; DPCM; HDTV; Schaltungstechnik

Prototype chips have been designed and fabricated which prove that a 2.5 micrometer BiCMOS process is feasible for implementation of DPCM coders operating at HDTV clock frequencies, i.e. 54 MHz. As a part of the DPCM, a BiCMOS sequencer with 64 product terms runs at 80 MHz with 125 mW power consumption.