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Title
Basiszelle fuer eine kanallose Gate-Array-Anordnung
Date Issued
1995
Author(s)
Tröster, Gerhard
Eßer, Wilfried
Rothermel, Albrecht
Schardein, Werner
Patent No
1990-4002780
Abstract
The invention relates to a basic cell for a channel-less gate array layout (''Sea of Gate'' (SOG) array) in a combined CMOS and bipolar technology, whereby each basic cell comprises at least one bipolar transistor and several metal-oxide semiconductor field effect transistors (MOSFET) whose gate electrodes each have two terminal areas located on the opposite side from the associated source drain area. According to the invention, a bipolar transistor, MOS field effect transistors of the first as well as of the second channel type are arranged in a central area of the basic cell, whereby on opposite sides of the central area, there are three parallel rows composed of several MOS field effect transistors. The first row is composed of oxide-insulated MOS field effect transistors of the first channel type, the second row is composed of gate-insulated MOS field effect transistors of the first channel type and the third row is also composed of gate-insulated MOS field effect transistors of th e second channel type. Furthermore, both terminal areas of the gate electrodes of the MOS field effect transistors of the first, second and third rows are placed in an offset arrangement to each other in a perpendicular orientation to the direction of the rows, whereby the gate electrodes are arranged with their terminal areas parallel to a row of associated MOS field effect transistors. ...
Language
de
Patenprio
DE 1990-4002780 A: 19900131