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Automatic synthesis of neural networks to programmable hardware

: Gick, S.; Heusinger, P.; Reuter, A.

Third International Conference on Microelectronics for Neural Networks 1993. Proceedings
Edinburgh, 1993
ISBN: 1-898273-00-6
International Conference on Microelectronics for Neural Networks (MICRONEURO) <3, 1993, Edinburgh>
Conference Paper
Fraunhofer IIS A ( IIS) ()
chip architecture; Chiparchitektur; digital implementation; digitale Implementierung; FPGA; neural network; neuronales Netzwerk; system architecture; Systemarchitektur; VHDL

A tool for automatic synthesis of neural network structures to programmable hardware components is introduced. Starting off with a simple textual specification of the neural network structure, containing the characteristics of the network like topology and synaptic weights, a complete hierarchical description of the corresponding hardware structure is automatically generated. Herefore, the hardware description language VHDL is used. Assisted by a VHDL testbench, which is automatically generated as well, the system can be simulated and functionally verified. Based on this VHDL description an optimized logic synthesis to a predefined FPGA target-technology is possible. By using a flexible bitserial arithmetic a compact implementation on-chip is achieved. The weight values for the synaptic multipliers are also integrated on the chip as combinatorial lookup tables. This system represents a powerful tool for realization of neural network structures that combines the speed of a pure hardware implementation with the flexibility of a software solution.