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ASICs for prototyping of pulse-density modulated neural networks

: Nijhuis, J.; Siggelkow, A.; Kesper, M.; Richert, P.; Schwarz, M.; Spaanenburg, L.

Ramacher, U.; Rückert, U.:
VLSI design of neural networks
Amsterdam: Kluwer Academic Publishers Group, 1991 (Kluwer international series in engineering and computer science 122)
ISBN: 0-7923-9127-6
Workshop on Microelectronics for Neural Networks <1, 1990, Dortmund>
Conference Paper
Fraunhofer IMS ()
application; ASIC; communication processor; emulator; gate array; hardware; multiprocessor system; neural network; neural processor; NNC; NNS; prototyping; pulse-density; router

Two alternative ways are presented for creating dedicated neural hardware realization based on pulse-density modulation. The first approach emphasizes fast prototyping of neural systems in a conventional digital microprocessor environment. It uses an ASIC cell library in combination with a sea-of-gates template to produce testable integrated neural circuits with off-chip learning. Typical single-chip network sizes range from 18 (eighteen) neurons with 846 (eighthundred and fourty-six) synapses to 110 (onehundred ten) neurons with 550 (fivehundred and fifty) synapses. Larger network sizes can be obtained by concatenation.