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1992
Conference Paper
Titel
Area and latency efficient CORDIC architectures
Abstract
The CORDIC algorithms has proved to be a powerful and flexible generic architecture to implement many signal processing and image processing algorithms. In practice, however, it sometimes suffers from its comparatively excessive silicon area demands. We present hardware solutions with reduced chip area requirements and power dissipation for parallel array or pipeline implementations of the unified algorithm (providing all known CORDIC functions) as well as for specialised architectures, supporting a subset of CORDIC functions. The chip area savings lie between 20% and 50%, respectively. In addition, these architectures result in lower latencies, typically by 25-50%, when compact non-redundant addition schemes like ripple-carry adders are employed.