Publica
Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten. A VLSI chip for wavelet image compression
| Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Symposium on Circuits and Systems 1999. Proceedings
Piscataway, NJ: IEEE, 1999
ISBN: 0-7803-5474-5
pp.IV/271-IV/274 |
| International Symposium on Circuits and Systems (ISCAS) <32, 1999, Orlando/Fla.> |
|
| English |
| Conference Paper |
| Fraunhofer IMS, Außenstelle Dresden ( IPMS) () |
| Bildkompression; chip; Digitale Photographie; VLSI; Wavelet-Transformation |
Abstract
We have designed a VLSI Chip for Wavelet Image compression which is especially suited for CCD area sensors as well as for new technology approaches in CMOS image sensors. The design has been developed for maximal resolutions of 3072 times 2048 pixels. The used compression algorithm gives a PSNR (peak signal to noise ratio) of up to 39 dB at 1bit/pixel for common test images.