Process for the production of a three-dimensional integrated circuit

Abstract
The invention relates to a process for the production of a three-dimensional integrated circuit. When joining the substrates which contain a large number of identical components, so-called chips, the resulting yield of a multi-layer system is obtained from the product of the individual yields. This leads to the fact that the yield of a system comprising several component layers is drastically reduced using known processes. In the process according to the invention, two finished substrates are joined together. Previously, however, the top substrate is subjected to a functional test, whereby the intact chips of the substrate are selected. Then this substrate is thinned from the rear, separated into individual chips and only selected, intact chips are applied justified on the bottom substrate which is provided with an adhesive coating. Using the process according to the process, the yield is drastically increased through the production of three-dimensional integrated circuits, and product ion costs are lowered.