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Verfahren zum Herstellen einer integrierten CMOS-Schaltung mit einem ISFET und mit einem Auswertungs-MISFET in Polysiliziumtechnologie

Process for the production of an integrated CMOS circuit comprising an ISFET and an evaluation MISFET in polysilicon technology
 
: Hein, P.; Ramm, P.

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Frontpage ()

DE 1991-4115397 A: 19910510
DE 1991-4115397 A: 19910510
DE 4115397 A1: 19921112
H01L0027
German
Patent, Electronic Publication
Fraunhofer IZM ()

Abstract
A process for the production of an integrated CMOS circuit having an ISFET and an evaluation MISFET in polysilicon gate technology comprises the process steps of generating isolation areas, generating a polysilicon gate, implementing source and drain, stripping an active gate area of the ISFET and applying a passivation layer. In order to adapt the electrical characteristics of the ISFET and the evaluation MISFET to each other, the process step of generating the gate isolator comprises the application of a gate nitride layer to the gate oxide layer and the process of stripping the active gate area of the ISFET comprises etching away the polysilicon gate down to the gate nitride layer acting as an etching stop.

: http://publica.fraunhofer.de/documents/PX-38852.html