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Utilizing coupled process and device simulation for optimization of sub-quarter-micron CMOS technology

Gekoppelte Prozeß- und Bauelementesimulation für die Optimierung der CMOS-Technologie unter 0,25 Mikrometer
 

Brebbia, C.A.; Konrad, A.:
Software for Electrical Engineering Analysis and Design IV
Southampton, U.K.: Computational Mechanics, 1999
ISBN: 1-85312-684-5
pp.181-190
ELECTROSOFT <4, 1999, Sevilla>
English
Conference Paper
Fraunhofer IIS B ( IISB) ()
Bauelementesimulation; CMOS-Technologie; CMOS technology; device simulation; Ioenenimplantation; ion implantation; Optimierung; optimization; process simulation; Prozeßsimulation

Abstract
Coupled process and device simulation was applied for the optimization of sub-quarter-micron CMOS technology. Optimum conditions for critical ion implantation steps were found. Especially it was shown that an increased implantation dose of the source and drain extensions improves the device performance. On this basis, the device performance achievable when shrinking to the $0.15 mu m$ generation of CMOS technology was estimated. Finally, an example of the coupled three-dimensional process and device simulation which indicates the role of 3D effects in small size CMOS transistors is presented.

: http://publica.fraunhofer.de/documents/PX-38124.html