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System architecture and key components for an 8 bit/1 GHz GaAs MESFET ADC

 

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Institute of Electrical and Electronics Engineers -IEEE-:
14th Annual GaAs IC Symposium 1992. Technical digest
New York/N.Y.: IEEE, 1992
ISBN: 0-7803-0773-9
ISBN: 0-7803-0774-7
ISBN: 0-7803-0775-5
pp.105-108
GaAs IC Symposium <14, 1992, Miami Beach, Fla.>
English
Conference Paper
Fraunhofer IIS A ( IIS) ()
Abtasthalteglied; ADC; ADU; Analog-Digital-Umsetzer; analog-to-digital-converter; DAC; DAU; Digital-Analog-Umsetzung; digital to analog converter; Gallium Arsenid; gallium arsenide; MESFET; T&H; track and hold circuit

Abstract
GaAs Analog to Digital Converters (ADC) published up to now are flash or parallel type converters. The maximum resolution that can be achieved with this approach is limited to 5 bit using today's GaAs MESFET technologies. Employing a parallel feedforward algorithm helps to overcome these architecture and technology limitations. Therefore, a two stage cascaded converter was selected for achieving 8Ebit resolution at 1 GHz sampling rate. Key components for this kind of converter have been developed, fabricated and characterized. Measurements of the Track & Hold circuitry (T & H) showed a droop of 3 mV/mu m, a slew rate of 3 kV/mu ms and a settling time of 220 ps. Its accuracy corresponds to 9.5 bit at 1 GHz clock rate with 100 MHz input frequency. The 4 bit quantizer operates up to 1.5 GSps. At 800 MSps, 3.8 effective bits were achieved with input frequencies up to 200 MHz. The integral non-linearity (INL) was better than 0.16 LSB. The Digital to Analog Converter (DAC) necessary to recon struct the analog signal after coarse quantization was merged into this quantizer to minimize the propagation delay of this path, which determines the maximum sampling rate.

: http://publica.fraunhofer.de/documents/PX-35529.html