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Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten. Reliability investigations of different bumping processes for flip chip and TAB applications
| Vardaman, E.J. ; Semiconductor Equipment and Materials International -SEMI-, San Jose/Calif.; IEEE Components, Packaging, and Manufacturing Technology Society:
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium 1996. Proceedings
Piscataway, NJ: IEEE, 1996
ISBN: 0-7803-3642-9
ISBN: 0-7803-3643-7
ISBN: 0-7803-3644-5
pp.274-281 |
| International Electronics Manufacturing Technology Symposium (IEMT) <19, 1996, Austin/Tex.> |
|
| English |
| Conference Paper |
| Fraunhofer IZM () |
| flip-chip devices; lead bonding; reliability; Soldering; tape automated bonding |
Abstract
Presently, a number of bump metallurgies are used for flip chip and TAB technology. However, no conclusive characterisation of the processes used and reliability obtained is available up to now. For wafer bumping, alloys of electroplated PbSn5, PbSn63, AuSn20 and metals like Au are used as well as electroless Ni(P)-Au deposition. Flexible bumping processes like Au stud bumping and mechanical bumping with PbSn solders on a solder wettable UBM are evaluated as alternatives, which are of essential importance for flip chip or TAB especially for small and medium volume applications. Reliability investigations on these used metallurgies are performed. The mechanical stability of the bumps is tested after thermal cycling, taking special care in the determination of the failure mode. Finally, the results are characterized, compared and evaluated.