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Reliability investigations for flip chip on flex using different solder materials



Electronic Industries Association -EIA-; IEEE Components, Packaging, and Manufacturing Technology Society:
48th Electronic Components and Technology Conference 1998. Proceedings
Piscataway/N.J.: IEEE Order Department, 1998
ISBN: 0-7803-4526-6
ISBN: 0-7803-4527-4
ISBN: 0-7803-4528-2
ISBN: 0-7803-4529-0
Electronic Components and Technology Conference (ECTC) <48, 1998, Seattle/Wash.>
Conference Paper
Fraunhofer IZM ()
ageing; chemical interdiffusion; circuit reliability; electroless deposited coatings; electroplated coatings; flip-chip devices; materials testing; mechanical testing; packaging; printed circuit manufacture; Soldering; surface mount technology; void

Flip chip assembly on flexible organic substrates is facing increasing interest. In consumer products such as mobile phones or pagers, the assembly of the drivers of the LCD displays can be realized this way. Also there is a growing demand for Chip Size Packages (CSP). As a low cost version, CSPs based on flexible interposers have been developed. Especially for this application the reliability of the assemblies is important. Little is known about the aging behavior of these packages with different solder materials such as Pb-Sn and Au-Sn on standard tape metallizations as Cu-Au or Cu-Ni-Au. The impact of the bumping technology on the reliability is also a subject. Electroplated bumps are studied in comparison with meniscus bumps. Based on electroless Ni bumping, this cost effective technology is especially suited for flip chip on flex as the solder volume deposited is very small. In order to make useful predictions about the reliability of a metallurgical system it is necessary to understand the basic reactions involved. The scope of the investigations presented in this paper is to gain the data on interdiffusion in these systems, on the formation and growth of intermetallic phases. The impact of the presence of intermetallics and voids on the mechanical reliability is determined. The test program includes annealing of the flip chip assemblies at different temperatures and thermal cycling. Electrical measurements (Daisy chain) and shear tests are performed to determine the electrical and mechanical degradation of the solder joints.