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Realization and evaluation of an ultra low-voltage/low-power 0.25 mu m (n+/p+) dual-workfunction CMOS technology

Realisierung und Evaluierung einer Niedervolt/Energiespar 0.25 mu m (n+/p+) Dual-Gate-CMOS-Technologie
: Schwalke, U.; Berthold, J.; Burenkov, A.; Eisele, M.; Krieg, R.; Narr, A.; Schumann, D.; Seibert, R.; Thanner, R.

Grünbacher, H.:
ESSDERC '97. Proceedings of the 27th European Solid-State Device Research Conference
Paris: Ed. Frontieres, 1997
ISBN: 2-86332-221-4
European Solid-State Device Research Conference (ESSDERC) <27, 1997, Stuttgart>
Conference Paper
Fraunhofer IIS B ( IISB) ()
Bauelemente-Simulation; CMOS-Technologie; CMOS technology; device simulation; Dual-Gate-Technologie; dual-gate technology; dünne Gateoxide; Energiesparelektronik; Low-Power; low voltage; process simulation; Prozeßsimulation; thin gate oxides

The ultimate goal for low power applications is aimed at single-battery operation with a nominal supply voltage of 1.2V and an end-of-life voltage of 0.9V. In this work results on process optimization, device characterization, dynamic performance and hot carrier degradation of an ultra low-power/low-voltage (1.2V) quarter-micron dual-workfunction CMOS technology with low process complexity are presented.