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A 50 V smart power process with dielectric isolation by SIMOX

 
: Vogt, H.; Weyers, J.

Institute of Electrical and Electronics Engineers -IEEE-:
International Electron Devices Meeting '92. Technical Digest
New York/N.Y.; Piscataway/N.J., 1992
ISBN: 0-7803-0817-4
pp.225-228
International Electron Devices Meeting <1992, San Francisco/Calif.>
English
Conference Paper
Fraunhofer IMS ()
CMOS process; CMOS-Technik; dielectric isolation; DMOS transistor; driver circuits; npn transistor; Schottky-Diode; SIMOX; Smart-power-Technik; smart power technology; Sperrschicht-FET; Treiberstufe; trenches

Abstract
A new process has been developed which provides dielectrically isolated power and low voltage devices by means of rather standard VLSI CMOS technology. Isolation is obtained by SIMOX and trenches. For smart power applications this process allows the manufacturing of 50 V vertical DMOS transistors (VDMOS) together with 50 V dielectrically isolated quasivertical DMOS transistors (QVDMOS). For control circuit design CMOS, high voltage PMOS transistors (HVPMOS), NPN transistors, JFETs, Zener and Schottky diodes are available on the same chip. Thus, the designer has at hand a wide range of devices which allows an optimun solution for many circuit applications.

: http://publica.fraunhofer.de/documents/PX-2912.html