10 Gbit/s low-power bit synchroniser with automatic retiming phase alignment.

A 10Gbit/s bit-synchroniser circuit has been fabricated using an enhancement/depletion 0.3Mym recessed-gate AlGaAs/GaAs/AlGaAs quantum well FET process. Te differential gain of the exclusive-or phase comparator circuit is measured to be 371 mV/rad. The phase margins for monotonous phase comparison are -54/plus21 degree relative to the "in bit cell centre" position of the negative going clock edge. The chip has a power dissipation of 160 mW when using a supply voltage of 1.90 V.