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10 Gbit/s low-power bit synchroniser with automatic retiming phase alignment.

10 Gbit/s Bit-Synchronisierer geringer Verlustleistung mit automatischer Takt-Anpassung
 

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Electronics Letters 27 (1991), No.17, pp.1529-1532 : Abb.,Lit.
ISSN: 0013-5194
English
Journal Article
Fraunhofer IAF ()
Bit-Synchronisierer; bit synchronizer; circuit design; Schaltungsentwurf

Abstract
A 10Gbit/s bit-synchroniser circuit has been fabricated using an enhancement/depletion 0.3Mym recessed-gate AlGaAs/GaAs/AlGaAs quantum well FET process. Te differential gain of the exclusive-or phase comparator circuit is measured to be 371 mV/rad. The phase margins for monotonous phase comparison are -54/plus21 degree relative to the "in bit cell centre" position of the negative going clock edge. The chip has a power dissipation of 160 mW when using a supply voltage of 1.90 V.

: http://publica.fraunhofer.de/documents/PX-2832.html