10 Gbit/s bit-synchronizer with automatic retiming clock alignement using Quantum Well AlGaAs/GaAs/AlGaAs technology

A 10 Gbit/s bit-synchronizer circuit has been fabricated using an enhancement/depletion 0.3 Mym recessed-gate AlGaAs/GaAs/ AlGaAs quantum well FET process. The differential gain of the phase comparator circuit is measured to be 371 mV/rad. The phase margins for monotonous phase comparison are minus54 /plus21 degree relative to the "in bit cell center" position of the clock edge. The chip has a power dissipation of 160 mW at a supply of 1.90 Volts.