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10-Gb/s bit-synchronizer circuit with automatic timing alignment by clock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs technology.

10 Gb/s Bit Synchronisier-Schaltung mit automatischem Timing Alignment mit Hilfe eines Clock-Phasen-Schiebers unter Verwendung der Quantum-Well AlGaAs/GaAs/AlGaAs Technologie

IEEE journal of solid-state circuits 27 (1992), No.10, pp.1347-1352 : Abb.,Lit.
ISSN: 0018-9200
Journal Article
Fraunhofer IAF ()
Bit-Synchronisierer; bit synchronizer; clock recovery; Clock Rückgewinnung; high-speed data communication; Hochgeschwindigkeitsdatenübertragung; opto-electronic data link; optoelektronische Datenverbindung; phase shifter; Phasenschieber

A bit-synchronizer circuit is presented which operates up to a bit rate of 10 Gb/s. The circuit comprises two master-slave flip-flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 392 mV/rad for a 1010 bit sequence. The margins for monotonous phase comparison are plusminus 54 degree relative to the "in bit cell center" position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3-Mym recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V.