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7.5 Gb/s monolithically integrated clock recovery using PLL and 0.3 mym gate length quantum well HEMTs

7.5 Gb/s monolithisch integrierte Schaltung zur Taktrückgewinnung mit der PLL-Technik und Quantum-Well-HEMTs der Gatelänge von 0.3 mym
 

ESSCIRC '93. 19th European Solid State Circuits Conference. Proceedings
Gif-sur-Yvette Cedex: Editions Frontieres, 1993
ISBN: 2-86335-134-X
pp.222-225 : Abb.,Lit.
European Solid State Circuits Conference (ESSCIRC) <19, 1993, Sevilla>
English
Conference Paper
Fraunhofer IAF ()
clock recovery; optical data transmission; optische Datentransmission; signal processing; Signalverarbeitung; Taktrückgewinnung

Abstract
A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with gate lengths of 0.3 mym has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO has been introduced. The VCO has a centre oscillating frequency of about 7.5 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at the bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at the supply voltage of -5 V.

: http://publica.fraunhofer.de/documents/PX-2814.html