• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Artikel
  4. Pattern matching and refinement hybrid approach to circuit comparison
 
  • Details
  • Full
Options
1994
Journal Article
Title

Pattern matching and refinement hybrid approach to circuit comparison

Abstract
We present a new approach to circuit comparison which was developed to combine general applicability with most of the advantages of hierarchical processing. Two reasons often prevent hierarchical cell by cell comparison: hierarchical circuit extraction cannot be performed in all cases and if so, the resulting hierarchy is often non-isomorphic to the schematic hierarchy. Therefore, general applicability requires the ability to cope with flat circuits. Consequently, many tools compare flat netlists of transistors or logic gates. On the other hand, apart from the speed-up, hierarchical processing is superior in terms of error localization and functional but not topological isomorphism. Our objective was to develop a tool which exploits the latter two advantages of hierarchical processing, while not sacrificing general applicability. The basic principle of operation is the pattern matching of arbitrary subcircuits in larger circuits.
Author(s)
Pelz, G.
Röttcher, U.
Journal
IEEE transactions on computer-aided design of integrated circuits and systems  
DOI
10.1109/43.259949
Language
English
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS  
Keyword(s)
  • comparison

  • computer-aided circuit design

  • microelectronics

  • Mikroelektronik

  • Mustererkennung

  • pattern matching

  • rechnerunterstützter Schaltungsentwurf

  • Vergleich

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024