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6-Bit 25 MHz NMOS parallel A/D converter

 
: Fiedler, H.-L.; Zimmer, G.

Electronics Letters 19 (1983), No.9, pp.348-349
ISSN: 0013-5194
English
Journal Article
Fraunhofer IMS ()

Abstract
A standard silicon gate NMOS enhanced/depletion process with 4 mym minimum channel length has been applied in the design of a 6-bit parallel A/D converter. The chip features a conversion rate of 25 MHz (MSPS), 8x5 MHz analogue input signal bandwidth and small chip size of 4x9 mm2.

: http://publica.fraunhofer.de/documents/PX-2808.html