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A 5-bit 150 MS/s, 3.3 V CMOS A/D converter with a 32 step adjustable reference ciruit

 
: Desel, T.; Kuttner, F.; Kropf, C.; Haas, M.

Grünbacher, H.:
ESSCIRC '97. Proceedings of the 23rd European Solid State Circuits Conference
Gif-sur-Yvette: Ed. Frontieres, 1997
ISBN: 2-86332-220-6
pp.240-243
European Solid State Circuits Conference (ESSCIRC) <23, 1997, Southampton>
English
Conference Paper
Fraunhofer IIS A ( IIS) ()
ADC; ADU; Analog-Digital-Umsetzer; analog to digital converter; low power; parallel

Abstract
A 5-bit 150 MS/s full-flash A/D converter with a 32 step adjustable reference circuit is presented. The fully differential architecture with integrated sample/hold circuit significantly improves the performance in a noisy environment. For compatibility a single ended input signals might also applied. This ADC is integrated in a standard 0.7 mm single poly, triple metal CMOS technology at 2.7 V to 3.7 V supply, and dissipates typically 85 mW. Excellent results are achieved with using no more than 0.9 mm2 .

: http://publica.fraunhofer.de/documents/PX-2804.html