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  4. A 5-bit 150 MS/s, 3.3 V CMOS A/D converter with a 32 step adjustable reference ciruit
 
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1997
Conference Paper
Title

A 5-bit 150 MS/s, 3.3 V CMOS A/D converter with a 32 step adjustable reference ciruit

Abstract
A 5-bit 150 MS/s full-flash A/D converter with a 32 step adjustable reference circuit is presented. The fully differential architecture with integrated sample/hold circuit significantly improves the performance in a noisy environment. For compatibility a single ended input signals might also applied. This ADC is integrated in a standard 0.7 mm single poly, triple metal CMOS technology at 2.7 V to 3.7 V supply, and dissipates typically 85 mW. Excellent results are achieved with using no more than 0.9 mm2 .
Author(s)
Desel, T.
Kuttner, F.
Kropf, C.
Haas, M.
Mainwork
ESSCIRC '97. Proceedings of the 23rd European Solid State Circuits Conference  
Conference
European Solid State Circuits Conference (ESSCIRC) 1997  
Language
English
IIS-A  
Keyword(s)
  • ADC

  • ADU

  • Analog-Digital-Umsetzer

  • analog to digital converter

  • low power

  • parallel

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