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A parallel DSP-based neural network emulator with CMOS VLSI paket switching hardware.

: Schwarz, M.; Hosticka, B.J.; Kesper, M.; Richert, P.; Scholles, M.

DOI: 10.1109/ASAP.1994.331787

	Cappello, P.; Owens, R.M.; Swarzlander, E.E.; Wah, B.W. ; IEEE Computer Society, Technical Committee on VLSI: International Conference on Application Specific Array Processors 1994 Los Alamitos: IEEE Computer Society Press, 1994 ISBN: 0-8186-6517-3 pp.381-391
	International Conference on Application Specific Array Processors <1994, San Francisco>

	English
	Conference Paper
	Fraunhofer IMS ()
	adaption; adaptive signal processing; anwenderspezifische integrierte Schaltung; ASIC; Biokybernetik; biological cybernetics; biological neural network; Echtzeitbetrieb; Emulation; hardware; neural emulator; neural hardware; neuronales Netzwerk; parallel computers; Parallelrechnersystem; real-time systems; Signalverzögerung; Systementwurf; systems design

Abstract
This work describes a parallel neural network emulator which uses standard DSPs and application-specific VLSI communication processors with an integrated hardware routing algorithm. The use of DSPs as programmable processing elements enables the emulation of different types of neurons including biologically inspired models with learnable synaptic weights and delays, variable neuron gain, and static and dynamic thresholding. Locally interconnected communication processors attached to each DSP can span up a 2D- or 3D-computing grid and thus form a highly parallel network topology capable of global packet switching routing.