Ein 2.5 ns 8x8-b Parallel-Multiplizierer mit 0.5 mym GaAs/GaAlAs Heterostruktur-Feld-Effekt Transistoren

: Hurm, V.; Nowotny, U.; Hülsmann, A.; Kaufel, G.; Raynor, B.; Schneider, J.; Berroth, M.; Köhler, K.

Abstract
To increase performace of GaAs LSI digital circuits, a 0,5 mym recessed gate process has been developed and utilized for an 8x8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.