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  4. A 2.5 ns 8x8-b parallel multiplier using 0.5 mym GaAs/GaAlAs heterostructure field effect transistors
 
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1991
Journal Article
Title

A 2.5 ns 8x8-b parallel multiplier using 0.5 mym GaAs/GaAlAs heterostructure field effect transistors

Other Title
Ein 2.5 ns 8x8-b Parallel-Multiplizierer mit 0.5 mym GaAs/GaAlAs Heterostruktur-Feld-Effekt Transistoren
Abstract
To increase performace of GaAs LSI digital circuits, a 0,5 mym recessed gate process has been developed and utilized for an 8x8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.
Author(s)
Hurm, V.
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Nowotny, U.
Hülsmann, A.
Kaufel, G.
Raynor, B.
Schneider, J.
Berroth, M.
Köhler, Klaus  
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Journal
Microelectronic engineering  
DOI
10.1016/0167-9317(91)90228-6
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Language
English
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Keyword(s)
  • DCFL

  • HFET

  • multiplier

  • Multiplizierer

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