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A 2.5 ns 8x8-b parallel multiplier using 0.5 mym GaAs/GaAlAs heterostructure field effect transistors

Ein 2.5 ns 8x8-b Parallel-Multiplizierer mit 0.5 mym GaAs/GaAlAs Heterostruktur-Feld-Effekt Transistoren


Microelectronic engineering 15 (1991), pp.327-330 : Abb.,Lit.
ISSN: 0167-9317
Journal Article
Fraunhofer IAF ()
DCFL; HFET; multiplier; Multiplizierer

To increase performace of GaAs LSI digital circuits, a 0,5 mym recessed gate process has been developed and utilized for an 8x8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.