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1991
Conference Paper
Titel
A 0.4 mym CMOS test circuit completely processed with 8-level X-ray lithography
Abstract
Sub-0.5 mym CMOS devices have been successfully fabricated by means of X-ray lithography at all levels. This paper reports about the X-ray lithography characterization, the CMOS technology including electrical device performance and the influence of radiation induced damages on the transistor behaviour. The overlay of subsequent lithography levels was determined equal or smaller than 180 nm, 3sigma with respect to X-ray mask copies with a mask distortion of 150 nm maximum. A linewidths variation in the poly-Si gate lavel of +- 50 nm could be achieved. The electrical devices have been characterized by static and dynamic measurements. NMOS and PMOS transistors exhibit no severe short channel effects for gate lengths down to 0.35 mym with a supply voltage of V sub D = 5 V.A stage delay time of 120 ps was measured at a 33 stage 0.45 mym CMOS ring oscillator. Radiation damages have been evaluated by comparison of X-ray and optically processed transistors and reveal no drastical differences.