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Investigations and measurements of the dynamic performance of high speed ADCs



IEEE transactions on instrumentation and measurement 41 (1992), No.6 Special Issue on Selected Papers IMTC/92, pp.829-833
ISSN: 0018-9456
Instrumentation and Measurement Technology Conference (IMTC) <9, 1992, New York/N.Y.>
Conference Paper
Fraunhofer IIS A ( IIS) ()
Abtasthalteglied; ADC; ADU; Analog-Digital-Umsetzer; analog-to-digital-converter; FET; Gallium Arsenid; gallium arsenide; T&H; track and hold circuit

The accuracy of ultra-high-speed analog-to-digital converters (ADCs) decreases at higher input frequencies. This is mainly due to timing mismatches, which cause the comparators to sample different time points of the input signal. Investigations concerning the origin of the aperture uncertainty in a 4-bit parallel ADC implemented in a 0.5 mu m GaAs FET technology were performed. On-chip E-beam measurements of the clock distribution for the comparators showed differences of 20 ps between the comparators. To overcome these problems, a GaAs 5-bit 1Egigasample per second (GSps) ADC with on-chip track-and-hold circuitry (T&H) was developed. A complete DC and AC characterization of the 5-bit ADC using a histogram test, Fast Fourier Transform test (FFT, sine wave curve fitting test and beat frequency test up to 1.3 GHz was performed. By using the T&H in front of the parallel ADC, 4.6 effective numbers of bits (ENOBs) are achieved at 1 GHz input signal compared to 3.7 ENOBs without T&H.