Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Integration of vertical/quasivertical DMOS, CMOS and bipolar transistors in a 50V SIMOX process

auch erschienen in: Microelectronic engineering 19 (1992)

Maes, H.E.; Mertens, R.P.:
ESSDERC '92. 22nd European Solid State Device Research Conference. Proceedings
Amsterdam, 1992
ISBN: 0-444-89478-0
pp.733 - 736
European Solid State Device Research Conference <22, 1992, Leuven>
Conference Paper
Fraunhofer IMS ()
50V SIMOX process; BCDMOS; bipolar transistor; Bipolartransistor; dielectric isolation; full bridge circuit drive; Leistungselektronik; MOS; QVDMOS; smart power; trenches; VDMOS

A new process has been developed that allows the production of dielectrically isolated power ICs by means of rather standard VLSI and BiCMOS technology on SIMOX substrates. Compared with processes like SDB, EPIC, soot bonding or MSSD this process is of less complexity as procedures like selective epitaxy or mechanical backlapping are not necessary. Furthermore, dielectric isolation permits higher inegration density, no latch up. less leakage current, high temperature operation, large noise immunity, easy circuit design and the integration of vertical DMOS transistors in contrast to conventional junction isolation. Compared with reproted junction isolation processes this technology even needs two masks less for the same variety of devices. Without process options only 11 masks are used.