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HOCHSPANNUNGSTRANSISTOR-ANORDNUNG IN CMOS-TECHNOLOGIE

High-voltage transistor setup in CMOS technology
 
: Zimmer, G.; Roth, W.; Seliger, S.; Winter, R. de

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Frontpage ()

DE 1988-3843644 A: 19881223
DE 1989-3936668 A: 19891103
EP 1990-900056 AW: 19891206
DE 3936668 C2: 19920903
EP 449858 B1: 19930505
H01L0027
German
Patent, Electronic Publication
Fraunhofer IMS ()

Abstract
The description refers to a high-voltage transistor arrangement in CMOS technology. In order to reach a dielectric strength in excess of 20 volts, DMOS (double diffused MOS) technology is used in known high-voltage transistor arrangements in which both source and drain zones aer surrounded by drift zones by means of a two-stage diffusion of doping atoms. This technology requires a production process with additional process steps. In the arrangement according to the invention, only the drain zone is surrounded by a drift zone, whereas the source zone is embedded directly in the semiconductor substrate. This permits the manufacture of the arrangement with the exclusive use of process steps taken from standard CMOS technology and no additional process steps. The high-voltage transistor arrangement according to the invention, having a dielectric strength in excess of 50 volts and, in special versions, in excess of 100 volts, is specially designed for use in automobile engineering and indus trial plants.

: http://publica.fraunhofer.de/documents/PX-17359.html