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  4. Extreme low power 1 to 4 demultiplexer using double delta doped Quantum Well GaAs/AlGaAs transistors.
 
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1990
Conference Paper
Title

Extreme low power 1 to 4 demultiplexer using double delta doped Quantum Well GaAs/AlGaAs transistors.

Other Title
1 zu 4 Demultiplexer mit extrem niedriger Leistungsaufnahme unter Verwendung von Doppel-Delta dotierten Quantum Well GaAs/AlGaAs Transistoren
Abstract
A 1:4 demultiplexer circuit has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.5 mym gate length based on a double-delta-doped- quantum well GaAs/AlGaAs structure. The process shows a gate delay of 25 ps at 0.5 mym gate length and 16 ps at 0.3 mym gate length. The demultiplexer was designed in Direct Coupled FET Logic (DCFL). First measurements show a data rate of 4 Gbit/s and a power consumption of 165 mW at 1.5V supply voltage, which is the lowest value published for comparable data rates. This includes five 50 Ohm buffers with 0.8V output voltage swing. A design using 0.3 mym gate length is in process.
Author(s)
Nowotny, U.
Hurm, V.
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Lang, M.
Kaufel, U.
Hülsmann, A.
Scheider, J.
Jakobus, T.
Bachem, K.H.
Berroth, M.
Hoffmann, C.
Köhler, Klaus  
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Mainwork
Extended Abstracts of the 22nd Conference on Solid State Devices and Materials  
Conference
Conference on Solid State Devices and Materials 1990  
Language
English
Fraunhofer-Institut für Angewandte Festkörperphysik IAF  
Keyword(s)
  • demultiplexer

  • fast data communication

  • fast digital electronics

  • HEMTs

  • Heterotransisitor

  • heterotransistor

  • low power

  • quantum well structures

  • schnelle Datenübertragung

  • schnelle Digitalelektronik

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