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Experimental verification of three-dimensional simulations of LTO layer deposition on structures prepared by anisotropic wet etching of silicon

 
: Bär, E.; Lorenz, J.; Ryssel, H.

:

Microelectronics reliability 38 (1998), No.2, pp.287-291
ISSN: 0026-2714
Dielectrics in Microelectronics Workshop <1996, Venice>
English
Conference Paper
Fraunhofer IIS B ( IISB) ()
chemical vapour deposition; etching; semiconductor process modelling; silicon compounds

Abstract
A simulator for the three-dimensional (3D) simulation of layer deposition has been developed. It allows the prediction of the shape of layers deposited on structured substrates. In this paper, thesimulation of low-temperature oxide (LTO) deposition is described. Model parameters reported in the literature were used to simulate LTO deposition at different process conditions. To allow quantitative comparison between experimental data and simulations, specific well-defined pyramidal test structures, which have been generated by anisotropic wet etching of silicon with potassium hydroxide (KOH), were used. The profiles of the concave edges of the topography as observed in the experiments were compared to those predicted by the 3D simulations. Good agreement was observed. This shows that the simulator allows the prediction of the geometry of deposited LTO layers. After implementation and calibration of additional models, further deposition systems can be simulated.

: http://publica.fraunhofer.de/documents/PX-13502.html