PublicaHier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.
Simulation assessment of process options for advanced CMOS devices
|IEEE Electron Devices Society; Forschungszentrum Jülich:|
10th International Conference on Ultimate Integration of Silicon, ULIS 2009 : March 18-20, 2009 - Aachen, Germany
New York, NY: IEEE, 2009
|International Conference on Ultimate Integration of Silicon (ULIS) <10, 2009, Aachen>|
| Conference Paper|
|Fraunhofer IISB ()|
| CMOS; MOSFET; process simulation; mechanical stress; RTA; contact resistances|
The simulation of process options for advanced CMOS devices is discussed in this work. Advanced rapid thermal annealing schemes are applied to fully depleted silicon on insulator MOSFETs with a physical gate length of 22 nm. Process induced mechanical stress is simulated for PMOS transistors to improve the Ion-Ioff relation. A modification of the linear piezo model is presented to simulate the hole mobility enhancement by mechanical stress. Contact resistances are reduced by using shallow contact trenches. Finally, the dynamic behavior is improved by replacing nitride spacers by oxide spacers.