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A framework for concurrency in numerical simulations using lock free data structures: The graph parallel architecture GraPA

 
: Klein, P.; Maleshkov, D.; Asenov, D.

:

Huang, Z. ; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society:
PDCAT 2008, Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies. Proceedings : Held in Dunedin, New Zealand from 1-4 of December, 2008
New York, NY: IEEE, 2008
ISBN: 978-0-7695-3443-5
ISBN: 978-1-4244-3660-6
pp.489-496
International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT) <9, 2008, Dunedin, New Zealand>
English
Conference Paper
Fraunhofer ITWM ()

Abstract
The development of numerical simulation software tools for the solution of real-world problems usually calls for domain experts in modeling. The GraPA framework,, as an abstraction layer on top of hardware characteristics, supports modelers in two respects: one is the built-in support for co-processing of multiple models and the other is the generically delivered high performance achieved by implementing concurrency features of multicore and distributed memory architectures. Technically, GraPA is designed as a C++ template framework, where the modeler's data structures and algorithms instantiate the framework. Using this approach, we handle parallel processing of lock-free data structures and message passing transperently to the modelers. In this paper, we report on the status of the implementation of GraPA and on its performance characteristics.

: http://publica.fraunhofer.de/documents/N-92358.html