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100 Gbit/s fully integrated InP DHBT-based CDR/1:2 DEMUX IC

100 GBit/s monolithisch integrierte InP-DHBT-basierende CDR/1:2 DEMUX Schaltung
: Makon, R.E.; Driad, R.; Lösch, R.; Rosenzweig, J.; Schlechtweg, M.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2008 : 12-15 Oct. 2008, Monterey/Calif.
Piscataway, NJ: IEEE, 2008
ISBN: 978-1-4244-1939-5
ISBN: 978-1-4244-1940-1
Compound Semiconductor Integrated Circuit Symposium (CSIC) <30, 2008, Monterey/Calif.>
Conference Paper
Fraunhofer IAF ()
InP double heterostructure bipolar transistor; InP-DHBT; integrated circuit; integrierte Schaltung; clock and data recovery; CDR; Takt- und Datenrückgewinnungsschaltung; half-rate linear phase detector; linearer Half-Rate-Phasendetektor; demultiplexer; DEMUX; loop filter; Schleifenfilter; voltage controlled oscillator; spannungsgesteuerter Oszillator; VCO

In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is presented. The integrated circuit (IC) is realized using an in-house InP double heterostructure bipolar transistor (DHBT) technology exhibiting cut-off frequency values of more than 300 GHz for both f(ind T) and f(ind max). The CDR IC consists mainly of a half-rate linear phase detector including a 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). A 100 Gbit/s data signal at the corresponding input of the CDR circuit gives rise to 50 Gbit/s recovered and demultiplexed output data featuring clear eye opening and a voltage swing of 500 mV(ind pp). The extracted 50 GHz clock signal from the input data features a voltage swing of 250 mV(ind pp), while the corresponding peak-to-peak (pp) and rms jitter amount to 2.1 ps and 0.5 ps, respectively. The full IC dissipates 2.1 W at a single supply voltage of -4.5 V.