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2008
Conference Paper
Titel
100 Gbit/s fully integrated InP DHBT-based CDR/1:2 DEMUX IC
Alternative
100 GBit/s monolithisch integrierte InP-DHBT-basierende CDR/1:2 DEMUX Schaltung
Abstract
In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX) is presented. The integrated circuit (IC) is realized using an in-house InP double heterostructure bipolar transistor (DHBT) technology exhibiting cut-off frequency values of more than 300 GHz for both f(ind T) and f(ind max). The CDR IC consists mainly of a half-rate linear phase detector including a 1:2 DEMUX, a loop filter, and a voltage controlled oscillator (VCO). A 100 Gbit/s data signal at the corresponding input of the CDR circuit gives rise to 50 Gbit/s recovered and demultiplexed output data featuring clear eye opening and a voltage swing of 500 mV(ind pp). The extracted 50 GHz clock signal from the input data features a voltage swing of 250 mV(ind pp), while the corresponding peak-to-peak (pp) and rms jitter amount to 2.1 ps and 0.5 ps, respectively. The full IC dissipates 2.1 W at a single supply voltage of -4.5 V.
Author(s)
Tags
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InP double heterostructure bipolar transistor
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InP-DHBT
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integrated circuit
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integrierte Schaltung
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clock and data recovery
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CDR
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Takt- und Datenrückgewinnungsschaltung
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half-rate linear phase detector
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linearer Half-Rate-Phasendetektor
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demultiplexer
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DEMUX
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loop filter
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Schleifenfilter
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voltage controlled oscillator
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spannungsgesteuerter Oszillator
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VCO