Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Interlayer cooling potential in vertically integrated packages

: Brunschwiler, T.; Michel, B.; Rothuizen, H.; Kloter, U.; Wunderle, B.; Oppermann, H.; Reichl, H.


Microsystem Technologies 15 (2009), No.1, pp.57-74
ISSN: 0946-7076
World Congress MicroNanoReliability <1, 2007, Berlin>
Journal Article, Conference Paper
Fraunhofer IZM ()

The heat-removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters <= 200 mu m. An experimental investigation with uniform and double-side heat flux at Reynolds numbers <= 1,000 and heat transfer areas of 1 cm(2) was carried out to identify the most efficient interlayer heat-removal structure. The following structures were tested: parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mu m and fluid structure heights of 100-200 mu m. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin in-line structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks having a 4-cm(2) heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from > 200 W/cm(2) at 1 cm(2) and > 50 mu m interconnect pitch to < 100 W/cm(2) at 4 cm(2). From experimental data, friction factor and Nusselt number correlations were derived for pin fin in-line and staggered structures.