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Pre-silicon SPICE modeling of nano-scaled SOI MOSFETs

Pre-Silicium SPICE Modellierung von nanoskalierten SOI MOSFETs
 
: Burenkov, A.; Kampen, C.; Lorenz, J.; Ryssel, H.

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Institute of Electrical and Electronics Engineers -IEEE-:
9th International Conference on Ultimate Integration of Silicon, ULIS 2008 : 12-14th March 2008, Udine, Italy
Udine, Italien: IEEE, 2008
ISBN: 978-1-4244-1729-2
pp.215-218
International Conference on Ultimate Integration of Silicon (ULIS) <9, 2008, Udine>
English
Conference Paper
Fraunhofer IISB ()
SPICE; CMOS; MOSFET; extraction

Abstract
Problems of pre-silicon compact modeling of nano-scaled silicon-on-insulator MOSFETs are addressed using the extraction of SPICE model parameters directly from numerical TCAD simulations. Although there are difficulties in the parameter extraction for the standard SPICE compact models we show by a direct comparison with the results of the numerical mixed-mode TCAD simulations that with some trade-offs in accuracy of static device characteristics reasonably accurate transient SPICE simulations are possible for such transistors.

: http://publica.fraunhofer.de/documents/N-77640.html