Options
2007
Conference Paper
Titel
DAVID - A strategic research project for chip-scale MEMS/ASIC co-integration
Alternative
DAVID - ein strategisches Forschungsprojekt für MEMS/ASIC-Systemintegration im Chip-Maßstab
Abstract
A hybrid wafer level packaging approach is presented that targets basically the industrial high-volume production of inertial measurement units. In a joint effort of six renowned European partners under the FP6 project DAVID, key technologies like post-CMOS through-silicon vias, vacuum compliant chip-to-wafer bonding and wafer level transfer molding are developed. The objective is a Chip-Scale System-in-Package (CSSiP) solution that can be implemented with a moderate effort and thus allows a realization of smart sensor systems in a short loop between design and manufacturing. Individual design and manufacturing steps are discussed: the optimal 4x4 mm2 size for the inertial sensor and possibilities of size reduction, the C2W (Chip-to-Wafer) process with two succesive steps, a pre-fixation of each single die on the substrate wafer and the simultaneous final bonding step, the W2W (Wafer-to-Wafer) approach, the problems in the TSV (Through-Silicon Via) step with thermomechanical stress, the final encapsulation and possible cost reduction using wafer molding and solder balling or transfer molding, and design aspects in 3D ASIC/MEMS integration using FEM simulations for optimization. An ultra-fine leak test for monitoring the vacuum quality in the sensor based on an initial neon bombing has been developed. Further details can be found on http://www.david-project.eu.
Language
English