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Packaging design and testing for high temperature applications > 150 °C

: Schreier-Alt, T.; Rebholz, C.; Ansorge, F.


Institute of Electrical and Electronics Engineers -IEEE-:
International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2007 : London, United Kingdom, 15 - 18 April 2007
Piscataway, NJ: IEEE Service Center, 2007
ISBN: 1-4244-1106-8
ISBN: 1-4244-1105-X
ISBN: 978-1-4244-1105-4
7 pp.
International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems (EuroSimE) <8, 2007, London>
Conference Paper
Fraunhofer IZM ()
high temperature packaging; automotive industry; numerical simulation

The paper presents final results of a project called "High Temperature Packaging with New Technologies" (HotPaNTs) with a consortium of well known partners from semiconductor and automotive industry. The project investigated system reliability at junction tempertures up to 200°C experimentally and by numerical simulations. Focus is on assembly, reliability testing of packaging technologies and in line electrical testing of the components at high temperatures. The design phase was accompanied by thermal simulations. We compared several package types (e.g. Flip Chip, QFN paddle up / down, QFP) concerning their performance under static and dynamic thermal loading. In detail two QFN packages have been studied: "paddle down" with main thermal pathways junction / board and "paddle up" with main pathway junction / air. A test chip with internal heat generators and temperature sensors was packaged in both housing types and assembled on different test boards. By numerical simulations and comparison with IR picture recordings, optimized thermal design guidelines (thermal vias, heat spreaders..) could be found.