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Improved Analytical I-V model for polygonal-shape enclosed layout transistors

 
: Lopez, P.; Cabello, D.; Hauer, H.

:

Institute of Electrical and Electronics Engineers -IEEE-:
ECCTD 2007,18th European Conference on Circuit Theory and Design : August 26-30, Sevilla, Spain
New York, NY: IEEE, 2007
ISBN: 1-4244-1342-7
ISBN: 978-1-4244-1342-3
pp.755-758
European Conference on Circuit Theory and Design (ECCTD) <18, 2007, Sevilla>
English
Conference Paper
Fraunhofer IIS ()

Abstract
An improved analytical I-V model accounting for the influence of short-channel effects on radiation-tolerant doughnut transistors is presented. The model is validated using TCAD simulation of the devices. The impact of this layout style on the driving capability of the devices is also analyzed confirming that it is seriously compromised in the case of large channel transistors which, together with an increase in the layout area discourages its use. However, for short-channel devices the driving capability is improved. Experimental validation in a standard 0.18μm technology is under way.

: http://publica.fraunhofer.de/documents/N-74740.html