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Towards a robust design of electronics assemblies under fracture, delamination and fatigue aspects

 
: Auersperg, J.; Michel, B.

:

Vaidyanathan, K. ; Institute of Electrical and Electronics Engineers -IEEE-, Singapore Section; IEEE Components, Packaging, and Manufacturing Technology Society:
EPTC 2007, 9th Electronics Packaging Technology Conference. Vol.2 : 10 - 12 December 2007, Grand Copthorne Waterfront Hotel, Singapore
New York, NY: IEEE, 2007
ISBN: 1-4244-1324-9
ISBN: 978-1-4244-1324-9
pp.476-481
Electronics Packaging Technology Conference (EPTC) <9, 2007, Singapore>
English
Conference Paper
Fraunhofer ENAS ()
Fraunhofer IZM ()

Abstract
Design studies of electronic components on the basis of parameterized FE-models and DoE/RSM-approaches are more and more performed to optimize it at early phases of the product development process. That is why electronics components especially in the field of RF, optoelectronics, high temperature and power applications are often exposed to extreme thermal environmental conditions, mechanical shock and vibrations. Simultaneously, the well known thermal expansion mismatch problem of the several materials, residual stresses generated by several steps of the manufacturing process and various kinds of inhomogeneity attribute to interface delamination, chip cracking and fatigue of interconnects, in particular. The applied methodologies typically base on classical stress/strain strength evaluations or/and life time estimations of solder interconnects using modified Coffin-Manson approaches. Recent studies show also how the evaluation of mixed mode interface delamination phenomena, classical strength hypotheses along with fracture mechanics approaches and thermal fatigue estimation of solder joints can simultaneously be taken into account.

: http://publica.fraunhofer.de/documents/N-68210.html