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Stackable packages with integrated components

 
: Ostmann, A.; Neumann, A.; Jung, E.; Aschenbrenner, R.; Reichl, H.

:

Iyer, M.K. ; Institute of Electrical and Electronics Engineers -IEEE-, Singapore Section, Reliability CPMT EDS Chapter; Components, Packaging and Manufacturing Technology Society -CPMT-; International Microelectronics and Packaging Society -IMAPS-:
5th Electronics Packaging Technology Conference, EPTC 2003. Proceedings : 10 - 12 December 2003, Pan Pacific Hotel, Singapore
Piscataway, NJ: IEEE, 2003
ISBN: 0-7803-8205-6
ISBN: 0-7803-8206-4
pp.19-23
Electronics Packaging Technology Conference (EPTC) <5, 2003, Singapore>
English
Conference Paper
Fraunhofer IZM ()

Abstract
A technology for the integration of thin chips into build-up layers of organic substrates is under development. In order to improve the process, laser technology has been introduced for via drilling and interconnect structuring. Basic reliability tests of embedded chips were performed. For the realization of integrated resistors the deposition of ultra-thin electroless Ni layers is used. Also here laser ablation has been implemented for structuring. Finally an improved and simplified concept for the realization of stackable chip packages is presented.

: http://publica.fraunhofer.de/documents/N-67559.html