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  4. 13000 FPS Vision System-on-Chip with Mixed-Signal Compressed Sensing
 
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2021
Presentation
Title

13000 FPS Vision System-on-Chip with Mixed-Signal Compressed Sensing

Title Supplement
Paper presented at International Image Sensor Workshop, IISW 2021, September 20-23, 2021, Online Event
Abstract
This paper presents a monolithic high-speed VSoC (Vision-System-on-Chip) with three software-programmable 16-bit ASIPs (application-specific instruction-set processors), a 1024-fold column-parallel data path of charge-based convolution functionality, freely configurable A/D conversion, 8-bit processor elements with 128 bytes of RAM each, and asynchronously compressing output of sparse column data. While 3D integration allows for combining a sensor field in optimal technology with a digital processing chip, it increases chip development, manufacturing and testing costs. In this design, the classical monolithic integration approach is pursued to achieve a single-chip solution with good fill factor and competitive performance in a classical 180 nm 1P6M CIS technology. To demonstrate the advantageous compressed sensing approach for fast and low-latency image processing, an algorithm for laser sheet-of-light triangulation was implemented.
Author(s)
Döge, Jens  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Hoppe, C.
Reichel, P.
Peter, N.
Reichel, A.
Skubich, C.
Project(s)
cSoC-3D
Funder
Bundesministerium für Bildung und Forschung BMBF (Deutschland)  
Conference
International Image Sensor Workshop (IISW) 2021  
DOI
10.24406/publica-fhg-413485
File(s)
N-645858.pdf (797.18 KB)
Rights
Under Copyright
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
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