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Process simulation of fan-out wafer level packaging: Influence of material and geometry on warpage

 
: Dijk, M. van; Jaeschke, J.; Wittler, O.; Stegmaier, A.; Schneider-Ramelow, M.

:

Institute of Electrical and Electronics Engineers -IEEE-; International Microelectronics and Packaging Society -IMAPS-:
IEEE 8th Electronics System-Integration Technology Conference, ESTC 2020. Proceedings : September 15th to 18th, 2020, Vestfold, Norway
Piscataway, NJ: IEEE, 2020
ISBN: 978-1-7281-6293-5
ISBN: 978-1-7281-6294-2
ISBN: 978-1-7281-6292-8
pp.207-212
Electronics System-Integration Technology Conference (ESTC) <8, 2020, Online>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Warpage issues during the processing of System in Packages (SiPs), by means of Fan-Out Wafer Level Packaging (FO-WLP), is still a challenging task. The differences in thermal expansion coefficients of the dissimilar materials, as well as the cure-shrinkage of the polymers for encapsulation and redistribution layers (RDL, combination of Polyimide (PI) insulation layers and copper (Cu) conductive layers) result in stresses during the processing. These stresses lead to warpage effects, which should be kept within limits in order to guarantee good quality of subsequent process steps. As material suppliers can modify the properties of the highly filled Epoxy Mold Compound (EMC) materials by adding fillers or additives, the question still remains which properties are influencing the warpage behavior. A sensitivity study by means of numerical simulations is therefore performed, varying different material properties, as well as different standard wafer sizes.

: http://publica.fraunhofer.de/documents/N-639400.html