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Dry Etched through SiC Via (TSiCV) Process Analysis Using DOE Modeling

: MacKowiak, P.; Schiffer, M.; Scheider-Ramelow, M.; Lang, K.-D.


Institute of Electrical and Electronics Engineers -IEEE-:
IEEE 22nd Electronics Packaging Technology Conference, EPTC 2020 : 2nd-29th December 2020, Virtual Conference, Singapore
Piscataway, NJ: IEEE, 2020
ISBN: 978-1-7281-8912-3
ISBN: 978-1-7281-8911-6
ISBN: 978-1-7281-8910-9
Electronics Packaging Technology Conference <22, 2020, Online>
Conference Paper
Fraunhofer IZM ()

This paper describes the research on modelling the etching parameters of SiC using RIE. The experiments were performed using a design of experiments (DOE) with a total 78 experiments and D-efficiency of over 85.4 finding the most significant process parameters impacting the etch result. All experiments were carried out for three different via diameters. The evaluation of the via etching was performed using confocal microscopy and by cross sections of the SiC vias. Afterwards the model was verified with etching experiments show very good match with the prediction model. The deviation between the model and the verification was below 6%.