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Design and fabrication of 4h-Sic Mosfets with optimized JFET and p-body design

: Ni, W.; Wang, X.; Feng, C.; Xiao, H.; Jiang, L.; Li, W.; Wang, Q.; Li, M.; Schlichting, H.; Erlbacher, T.


Lu, M.:
Materials for Electronics : Selected peer-reviewed papers from the Asia-Pacific Conference on Silicon Carbide and Related Materials (APCSCRM 2019), July 17-20, 2019, Beijing, China
Zurich: TTP, 2020 (Materials Science Forum 1014)
ISBN: 978-3-0357-3642-7
Asia-Pacific Conference on Silicon Carbide and Related Materials (APCSCRM) <2019, Beijing>
Conference Paper
Fraunhofer IISB ()
economic and social effects; electric fields; fabrication; Gates (transistor); interface states; junction gate field effect transistors; MOSFET devices; silica; silicon oxide

In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide’s critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO2 and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm-2eV-1 at EC - EIT = 0.21 eV and channel mobility of 19.3 cm2/Vs at VGS = 20 V were obtained. The fabricated MOSFET’s on-resistance of 6.4 mΩcm2 was obtained with hexagonal cell structure which is very consistent with the simulation results.