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Panel Level Packaging - From Idea to Industrialization -

 
: Braun, T.; Becker, K.-F.; Hoelck, O.; Voges, S.; Boettcher, L.; Töpper, M.; Stobbe, L.; Aschenbrenner, R.; Voitel, M.; Schneider-Ramelow, M.; Lang, K.-D.

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Institute of Electrical and Electronics Engineers -IEEE-:
IEEE CPMT Symposium Japan, ICSJ 2019 : November 18 - 20, 2019, Kyoto, Japan
Piscataway, NJ: IEEE, 2019
ISBN: 978-1-7281-0978-7
ISBN: 978-1-7281-0979-4
pp.85-87
IEEE CPMT Symposium Japan (ICSJ) <2019, Kyoto>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Drivers for 3D packaging solutions are manifold and each requirement calls for different answers and technologies. Main goal is miniaturization, but component density and performance, simplification of design and assembly, flexibility, functionality and finally, cost and time-to-market have been found to be the core drivers for going 3D as well. Besides die and package stacking, embedding dies is a key technology for heterogeneous system integration. There are two main approaches for embedded die technologies: Fan-out Wafer and Panel Level integration, where dies are embedded into polymer encapsulants and Chip in Polymer, where dies are embedded into the substrate.

: http://publica.fraunhofer.de/documents/N-629194.html