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A 1.8-V 91-dB DR second-order Sigma Delta modulator in 0.18 µm CMOS technology

: Carrillo, J.M.; Montecelo, M.A.; Neubauer, H.; Hauer, H.; Duque-Carillo, J.F.


Analog Integrated Circuits and Signal Processing 53 (2007), No.2-3 = Special sections on Selected Papers from DCIS 2005 and DTIP 2006, pp.63-69
ISSN: 0925-1030
ISSN: 1573-1979
Conference on Design of Circuits and Integrated Systems (DCIS) <20, 2005, Lisboa>
Journal Article, Conference Paper
Fraunhofer IIS ()

This paper deals with the implementation of a second-order Sigma Delta modulator in 0.18-mu m CMOS technology. The analog-to-digital converter structure combines a 1-bit approach along with a high oversampling ratio (OSR). A silicon circuit prototype, including the modulator itself, a current reference, and the clock signals generator, was designed to operate with a 1.8-V supply, fabricated and tested. Measured values of 87 dB and 91 dB were obtained for the signal-to-noise-plus-distortion ratio (SNDR) and the dynamic range (DR), respectively, for a clock frequency of 8 MHz and an OSR of 256. The effective number of bits (ENOB) was above 14. The experimental performance of the Sigma Delta modulator maintains a good level over a modulator clock range higher than 16 MHz, featuring an ENOB equal to 13 at 16 MHz.