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Degradation modeling and validation - bottlenecks for standard use of aging simulations in IC design

Paper presented at IEEE Automotive Reliability and Test Workshop, ART 2020, 5-6 November 2020, Virtual Conference
: Lange, André; Jancke, Roland

Postprint urn:nbn:de:0011-n-6181258 (962 KByte PDF)
MD5 Fingerprint: 66f7b34b0638aa1a9ac86f2b8669ce7e
Created on: 9.12.2020

2020, 4 pp.
Automotive Reliability and Test Workshop (ART) <2020, Online>
European Commission EC
100375234; ARAMID
radAR für AutonoMes fahren - eInsetzbar von jeDermann
Bundesministerium fur Wirtschaft und Energie BMWi (Deutschland)
Entwicklung eines Standards für ein elektronisches Datenformat zur Beschreibung von Mission Profiles
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
aging simulation; degradation model; transistor reliability; qualification; validation

Qualification according to the industry-standard AEC-Q100 is state of the art to verify the reliability of integrated circuits that are applied in automotive electronics. However, there are indications that this will not be sufficient for future applications. Instead, simulation-based reliability assessments in IC and system development are intended to complement qualification and allow efficient investigations of product reliability. Aging simulations for analog circuits have been available for years but appear to be hardly used. This article outlines degradation models and validation as bottlenecks that have to be overcome to establish aging simulations as a standard verification step in the future.